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A 300 mV, low power VCO with the central Frequency of 4.89 GHz in 22 nm FDSOI

 
: Kumar, P.; Böhme, E.; Al-Eryani, J.; Bora, P.P.; Borggreve, D.; Maurer, L.

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Institute of Electrical and Electronics Engineers -IEEE-:
IEEE Asia-Pacific Microwave Conference, APMC 2019. Proceedings : 10-13 December 2019, Marina Bay Sands, Singapore
Piscataway, NJ: IEEE, 2019
ISBN: 978-1-7281-3516-8
ISBN: 978-1-7281-3517-5
ISBN: 978-1-7281-3518-2
S.1378-1380
Asia-Pacific Microwave Conference (APMC) <2019, Marina Bay Sands/Singapore>
European Commission EC
H2020; 692477; REFERENCE
Rf Engineered substrates to FostER fEm performaNCE
European Commission EC
H2020; 783127; OCEAN12
Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node
Englisch
Konferenzbeitrag
Fraunhofer EMFT ()
5G; wideband; FDSOI; VCO; back-gate bias; IoT; low power

Abstract
A test circuit is presented which generates a frequency spectrum from 4.28 GHz to 5.5 GHz with the tuning percentage of 24.9%. The blocks presented in this paper consists of a Voltage controlled oscillator VCO, interfaced with differential divide by 2, a 2:1 Multiplexer and an output Buffer. All the sub-blocks are designed in 22-nm fully depleted Silicon-on-Insulator (SOI) CMOS technology. In this paper, the architectural design details, simulation and measurement results are presented. The VCO-core operates at the minimum supply voltage of 300 mV, with back-gate-bias voltage of 500 mV and consumes 0.48 mW power. The divided-signal exhibits phase noise performance of -114 dBc/Hz @ 1MHz offset when measured at the central frequency of 5.3 GHz FoMT of -192.7 dBc/Hz.

: http://publica.fraunhofer.de/dokumente/N-603157.html