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13-Gb/s Transmitter for Bunch of Wires Chip-to-Chip Interface Standard

: Chaudhary, Muhammad Waqas; Heinig, Andy; Choubey, Bhaskar

Postprint urn:nbn:de:0011-n-6030768 (975 KByte PDF)
MD5 Fingerprint: 50781fc59c76a2b4b568b20d0f97b075
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Erstellt am: 24.9.2020

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 : August 9 - 12, 2020, Springfield, MA, USA, On-line Proceedings
Piscataway, NJ: IEEE, 2020
ISBN: 978-1-7281-8058-8
ISBN: 978-1-7281-8059-5
ISBN: 978-1-5386-2916-1
International Midwest Symposium on Circuits and Systems (MWSCAS) <63, 2020, Online>
European Commission EC
10037523; ARAMID
radAR für AutonoMes fahren - einsetzbar für jeDermann
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
bunch of wires; Co-Design; interconnect; multi-chip communication; transmitter

Continuous downscaling of integrated circuits has reached a bottleneck. Technologies such as system in a package, multi-chip module and integration of chips on an active or passive interposer can further improve the system performance. Bunch of wires interface standard was recently introduced for chip to chip short interfaces within a package. This standard required both terminated and unterminated driver topologies for different data rates and interconnect lengths. This paper presents a first ever reported transmitter implementation of this interface. Unterminated and terminated impedance controlled drivers with feedback calibration enable transmitter power optimization for a given interconnect based on the respective signal integrity at the receiver side. Results show that this transmitter can support both low and high speed low power communication between chips for interconnects up to 11mm length with energy consumption of 0.34pJ/bit at maximum data rate of 13Gb/s. The transmitter is designed and taped out in 22nm FDSOI technology node.