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Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration

 
: Porteau, M.-L.; Gharbi, A.; Brianceau, P.; Dallery, J.-A.; Laulagnet, F.; Rademaker, G.; Tiron, R.; Engelmann, Hans-Jürgen; Borany, Johannes von; Heinig, Karl-Heinz; Rommel, Mathias; Baier, Leander

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Volltext ()

Micro and nano engineering 9 (2020), Art. 100074, 5 S.
ISSN: 2590-0072
European Commission EC
H2020; 688072; IONS4SET
Ion-irradiation-induced Si Nanodot Self-Assembly for Hybrid SET-CMOS Technology
Englisch
Zeitschriftenaufsatz, Elektronische Publikation
Fraunhofer IISB ()
single-electron-transistor; multilayer nanopillars; Si nanodots; e-beam lithography; ICP-RIE; EFTEM

Abstract
SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.

: http://publica.fraunhofer.de/dokumente/N-599853.html