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Influence of Shallow Pits and Device Design of 4H-SiC VDMOS Transistors on In-Line Defect Analysis by Photoluminescence and Differential Interference Contrast Mapping

 
: Kocher, Matthias; Schlichting, Holger; Kallinger, Birgit; Rommel, Mathias; Bauer, Anton J.; Erlbacher, Tobias

:

Yano, H.:
18th International Conference on Silicon Carbide and Related Materials, ICSCRM 2019 : Kyoto, Japan, September 29 to October 4, 2019
Durnten-Zurich: TTP, 2020 (Materials Science Forum 1004)
S.299-305
International Conference on Silicon Carbide and Related Materials (ICSCRM) <18, 2019, Kyoto>
Englisch
Konferenzbeitrag
Fraunhofer IISB ()
photoluminescence; Differential Interference Contrast; yield; VDMOS

Abstract
In this study, UV Photoluminescence (UVPL) and Differential Interference Contrast (DIC) mapping was applied for process control of a 1.2 kV 4H-SiC VDMOS fabrication process at different process stages in order to investigate the influence of shallow pits on the electrical behavior of the devices. In particular, it could be shown that UVPL and DIC mapping allows the correlation of shallow pits and the occurrence of darker regions in the UVPL images and distinguishing differently implanted regions at distinct process stages. By comparing the darker regions of the UVPL scan with the electrical blocking characteristics of the associated devices a direct correlation between the occurrence of shallow pits and the reduction of the blocking capability of the devices could be observed.

: http://publica.fraunhofer.de/dokumente/N-597039.html