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A 10.5 μW programmable SAR ADC Frontend with SC Preamplifier for Low-Power IoT Sensor Nodes

Paper presented at IEEE 6th Virtual World Forum on Internet of Things, WF-IoT 2020, 2-6 June 2020
: Jotschke, Marcel; Carvajal Ossa, Wilmar; Reich, Torsten; Mayr, Christian

Postprint urn:nbn:de:0011-n-5958144 (1.8 MByte PDF)
MD5 Fingerprint: e7dcd70bea80e404d16f0701812d03ca
Erstellt am: 10.7.2020

2020, 6 S.
World Forum on Internet of Things (WF-IoT) <6, 2020>
Fraunhofer-Gesellschaft FhG
Towards Zero Power Electronics
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
SAR ADC; analog frontend; Ultra low power; harvester-powered autonomous sensor node

Massive deployment of wireless autonomous sensor nodes requires their lifetime extension and cost reduction. The analog frontend (AFE) plays a key role in this context. This paper presents a successive approximation register analog-to-digital converter (SAR ADC) with a switched-capacitor programmable gain switched preamplifier (SC PGSA), as a basic component of an integrated ultra-low power AFE. AFE resolution, sample rate and signal gain are configurable between 6 to 13 bit, 1 to 10 kS/sand -6 to 12 dB, respectively. The circuit draws 10.5μW from a1.8V standard supply voltage, achieving an effective number of bits of 12.6 bit and a Walden figure of merit of 169.1 fJ/st. and30.6 fJ/st., computed with and without preamplifier, respectively. The circuit is employed in a modular internet of things sensor node, suitable to be solely powered from micro energy sources(energy harvesters). In order to feed charge-scaling SARADC inputs with the sensor voltages, typically a preamplifier stage is implemented, which can create energy overhead of magnitudes larger than the ADC power. This paper presents a duty-cycled preamplifier with programmable gain for SAR ADCs, utilizing switched-capacitor switched-opamp technique in the SC PGSA. No additional buffer circuitry is needed to charge the SAR ADC, and the preamplifier design is relaxed in power constraint. The circuit targets the low-cost internet of things market. Cost efficiency is achieved by technology choice, wide configurability and shortened ASIC design cycles. The latter results from partly generated layout, easing reuse of circuit parts from a different CMOS node. A test chip in a low-cost 180nm silicon-on-insulator technology was fabricated.