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Analysis of flip-chip solder joints under isothermal vibration loading

 
: Meier, Karsten; Leslie, David; Dasgupta, Abhijit; Röllig, Mike; Bock, Karlheinz

:

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 21st Electronics Packaging Technology Conference, EPTC 2019 : 4-6 December 2019, Singapore
Piscataway, NJ: IEEE, 2019
ISBN: 978-1-7281-3835-0
ISBN: 978-1-7281-3834-3
ISBN: 978-1-7281-3836-7
S.138-142
Electronics Packaging Technology Conference (EPTC) <21, 2019, Singapore>
Englisch
Konferenzbeitrag
Fraunhofer IKTS ()
Soldering; sensors; fatigue; strain; vibration; resonant frequency; substrates

Abstract
This work focuses on the reliability needs which are caused by the use of recent package solutions for harsh environmental use cases such as assisted or autonomous driving. Simultaneous thermal and mechanical loading of highly integrated packages as Flip-Chip (FC) packages has to be considered, investigated and understood. An earlier introduced test approach used to investigate CR0805 solder joints under combined loading was modified to enable the analysis of FC solder joints. Thus, investigations of solder joint geometries of FC, CSP and BGA packages are now possible. In this work, results on the fatigue behaviour of SnAgCu FC solder joints will be shown. The experiments were conducted under varied harmonic vibration amplitudes at room temperature. A 4.6 x 2.6 mm 2 bare die FC package with a 5 x 5 interconnection grid was tested. Bump size, pad diameter and stand-off are 370 μm, 330 μm and 280 μm , respectively. The damage and fatigue behaviour of the FC solder joints was examined using cross sections. First, test results show damage of solder joints stressed with a peak-to-peak deflection of 1.6 mm for up to 75 Million cycles at room temperature. The damage occurred within the solder volume in very close proximity to or at the substrate pad intermetallic interface. Further tests considering varied stress levels are ongoing.

: http://publica.fraunhofer.de/dokumente/N-589192.html