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A Fast and Stable Time Locked Loop for Network Time Synchronization with Parallel FLL and PLL

: Andrich, C.; Bauer, J.; Grosse, P.; Ihlow, A.; Galdo, G. del


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Instrumentation and Measurement Society:
ISPCS 2018, International IEEE Symposium on Precision Clock Synchronization for Measurement, Control, and Communication. Symposium Proceedings : September 30 - October 5, 2018, Genf, Switzerland
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-4263-4
ISBN: 978-1-5386-4262-7
ISBN: 978-1-5386-4264-1
International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPSC) <12, 2018, Genf>
Fraunhofer IIS ()

We propose a concept for accurate network time synchronization. In comparison to NTPv4 and PTPd, which use a closed-loop design with a single loop filter, our approach splits the task into two fundamental aspects: First, matching the local clock's frequency to the reference frequency is enforced (syntonization). Second, the remaining constant offset between both clocks is minimized (synchronization). We suggest syntonization with a frequency locked loop (FLL) using an open-loop design and synchronization with an additional feedback phase locked loop (PLL). This concept of a time locked loop is advantageous, as it allows faster clock synchronization (smaller settling times) compared to a joint closed-loop design, while furthermore avoiding transient oscillations.