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Microfluidic Interposer for High Performance Fluidic Chip Cooling

 
: Steller, W.; Windrich, F.; Bremner, D.; Robertson, S.; Mroßko, R.; Keller, J.; Brunschwiler, T.; Schlottig, G.; Oppermann, H.; Wolf, M.J.; Lang, K.-D.

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TU Dresden, Institut für Aufbau- und Verbindungstechnik der Elektronik -IAVT-; Institute of Electrical and Electronics Engineers -IEEE-; International Microelectronics and Packaging Society -IMAPS-:
7th Electronic System-Integration Technology Conference, ESTC 2018. Proceedings : 18th to 21st Sept. 2018, Dresden, Germany
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-6814-6
ISBN: 978-1-5386-6813-9
ISBN: 978-1-5386-6815-3
S.925-932
Electronic System-Integration Technology Conference (ESTC) <7, 2018, Dresden>
Englisch
Konferenzbeitrag
Fraunhofer IZM ()

Abstract
High operation temperatures are a main impact factor for long-term reliability. An efficient cooling approach is crucial especially for high performance computing processors (HPC). As reference, the “International Technology Roadmap for Semiconductors” (ITRS) predicted a power consumption of about 700W for data center server processors. Different cooling approaches were investigated already. Unfortunately, current solutions are not sufficient to fulfill high thermal HPC specifications. On one hand, the insufficient cooling performance is raising the chip junction temperature over the critical point. On other hand, the high performance requirements (e.g. low latency time, higher bandwidth) force to use 3D-Integration of components, which is additional raising the heat build-up. Therefore, only the direct integration of a cooling approach within the 3D-stack can eliminate the overheating bottleneck at all. The fluidic cooling approach has a high potential to fulfill the requirements for this direct fluidic integration approach. This work shows the integration and realization of microfluidic features (microfluidic channels and fluidic inlets/outlets) into an interposer. Furthermore we present the integration of this fluidic interposer into a System in Package (SiP) in order to realize a dual side chip cooling for a heat dissipation of 672W (168W/cm -2 which correlates with predicted power consumption of data center server processor according ITRS-Roadmap.

: http://publica.fraunhofer.de/dokumente/N-581482.html