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FPGA-based lens undistortion and image rectification for stereo vision applications

 
: Junger, C.; Heß, A.; Rosenberger, M.; Notni, G.

:

Rosenberger, M. ; Society of Photo-Optical Instrumentation Engineers -SPIE-, Bellingham/Wash.:
Photonics and Education in Measurement Science 2019 : 17-19 September 2019, Jena, Germany
Bellingham, WA: SPIE, 2019 (Proceedings of SPIE 11144)
ISBN: 978-1-5106-2981-3
ISBN: 978-1-5106-2982-0
Paper 1114416, 8 S.
Conference "Photonics and Education in Measurement Science" <2019, Jena>
Englisch
Konferenzbeitrag
Fraunhofer IOF ()

Abstract
Lens undistortion and image rectification is a commonly used pre-processing, e.g. for active or passive stereo vision to reduce the complexity of the search for matching points. The undistortion and rectification is implemented in a field programmable gate array (FPGA). The algorithm is performed pixel by pixel. The challenges of the implementation are the synchronisation of the data streams and the limited memory bandwidth. Due to the memory constraints, the algorithm utilises a pre-computed lossy compression of the rectification maps by a ratio of eight. The compressed maps occupy less space by ignoring the pixel indexes, sub-sampling both maps, and reducing repeated information in a row by forming differences to adjacent pixels. Undistorted and rectified images are calculated once without and once with the compressed transformation map. The deviation between the different computed images is minimal and negligible. The functionality of the hardware module, the decompression algorithm and the processing pipeline are described. The algorithm is validated on a Xilinx Zynq-7020 SoC. The stereo setup has a baseline with 46 mm and non-converged optical axis between the cameras. The cameras are configured at 1.3 Mpix @ 60 fps and distortion correction and rectification is performed in real time during image capture. With a camera resolution of 1280 pixels × 960 pixels and a maximum vertical shift of ± 20 pixels, the efficient hardware implementation utilizes 12 % of available block RAM resources.

: http://publica.fraunhofer.de/dokumente/N-574800.html