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XMSS and Embedded Systems

XMSS Hardware Accelerators for RISC-V
 
: Wang, Wen; Jungk, Bernhard; Wälde, Julian; Deng, Shuwen; Gupta, Naina; Szefer, Jakub; Niederhagen, Ruben

:

Paterson, Kenneth G.:
Selected Areas in Cryptography - SAC 2019 : 26th International Conference, Waterloo, ON, Canada, August 12-16, 2019. Revised Selected Papers
Cham: Springer, 2020 (Lecture Notes in Computer Science 11959)
ISBN: 978-3-030-38470-8 (Print)
ISBN: 978-3-030-38471-5
S.523-550
International Conference on Selected Areas in Cryptography (SAC) <26, 2019, Waterloo>
National Science Foundation NSF
1716541
Englisch
Konferenzbeitrag
Fraunhofer SIT ()
XMSS; hash-based signatures; post-quantum cryptography; hardware accelerator; FPGA; RISC-V

Abstract
We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We provide software optimizations for the XMSS reference implementation for SHA-256 parameter sets and several hardware accelerators that allow to balance area usage and performance based on individual needs. By integrating our hardware accelerators into the RISC-V processor, the version with the best time-area product generates a key pair (that can be used to generate 210 signatures) in 3.44 s, achieving an over 54× speedup in wall-clock time compared to the pure software version. For such a key pair, signature generation takes less than 10 ms and verification takes less than 6 ms, bringing speedups of over 42× and 17× respectively. We tested and measured the cycle count of our implementation on an Intel Cyclone V SoC FPGA. The integration of our XMSS accelerators into an embedded RISC-V processor shows that it is possible to use hash-based post-quantum signatures for a large variety of embedded applications.

: http://publica.fraunhofer.de/dokumente/N-574683.html