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Fast validation of DRAM protocols with timed petri nets

: Jung, Matthias; Kraft, Kira; Soliman, Taha; Sudarshan, Chirag; Weis, Christian; Wehn, Norbert


Association for Computing Machinery -ACM-:
International Symposium on Memory Systems, MEMSYS 2019. Proceedings : Washington, DC, USA, September 30 - October 03 2019
New York: ACM, 2019
ISBN: 978-1-4503-7206-0
International Symposium on Memory Systems (MEMSYS) <2019, Washington/DC>
Deutsche Forschungsgemeinschaft DFG
Fraunhofer IESE ()
DRAM; Memory Controller; Petri Net; Validation

In recent years, an increasing number of different JEDEC memory standards, like DDR4/5, LPDDR4/5, GDDR6, Wide I/O2, HBM2, and NVDIMM-P have been specified, which differ significantly from the previous ones like DDR3 and LPDDR3. Since each new standard comes with significant changes in the DRAM protocol compared to the previous ones, the developers of memory controllers and memory simulation models regularly face challenges implementing and verifying these new standards. In order to keep pace with these frequent changes of the requirements and the large variety of variants a robust validation methodology must be established. The JEDEC standards describe the complex memory protocol, i.e., DRAM commands and their timing dependencies, by using a mixture of state machine diagrams, tables, and timing diagrams. However, there exists no unique formal description of the JEDEC standards which could be used for a fast simulation-based validation. In this paper, for the first time, we present a comprehensive and formal mathematical model based on Petri Nets that contains the DRAM states, transitions, and timings. Furthermore, we present a Domain Specific Language (DSL) for describing the memory functionality and timing dependencies of a JEDEC standard in just a few lines of code. From this DSL description an executable Petri Net is generated automatically, which is used for the fast simulation-based validation of memory controllers and DRAM simulation models.