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Test circuits for fast and reliable assessment of CDM robustness of I/O stages

 
: Stadler, W.; Esmark, K.; Reynders, K.; Zubeidat, M.; Graf, M.; Wilkening, W.; Willemen, J.; Qu, N.; Mettler, S.; Etherton, M.; Nuernbergk, D.; Wolf, H.; Gieser, H.; Soppa, W.; Heyn, V. de; Natarajan, M.; Groeseneken, G.; Morena, E.; Stella, R.; Andreini, A.; Litzenberger, M.; Pogany, D.; Gornik, E.; Foss, C.; Konrad, A.; Frank, M.

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Microelectronics reliability 45 (2005), Nr.2, S.269-277
ISSN: 0026-2714
Englisch
Zeitschriftenaufsatz
Fraunhofer IZM ()

Abstract
CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, very-fast TLP tests, transient interferometric mapping, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.

: http://publica.fraunhofer.de/dokumente/N-57053.html