Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

A pseudo-complementary GaN-based gate driver with Reduced Static Losses

: Basler, Michael; Mönch, Stefan; Reiner, Richard; Waltereit, Patrick; Quay, Rüdiger; Kallfass, Ingmar; Ambacher, Oliver


Veliadis, Victor (ed.) ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Power Electronics Society:
7th IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2019 : October 29-31, 2019, Raleigh, North Carolina
Piscataway, NJ: IEEE, 2019
ISBN: 978-1-7281-3760-5
ISBN: 978-1-7281-3761-2
ISBN: 978-1-7281-3762-9
Workshop on Wide Bandgap Power Devices and Applications (WiPDA) <7, 2019, Raleigh/NC>
Fraunhofer IAF ()
gallium nitride; HEMTs; E-Mode; D-Mode; integrated circuits; logic circuits; nMOS; driver circuits

This work presents an approach of a normally-off gate driver with reduced static losses based on a n-channel GaNon-Si technology. The gate driver uses an additional GaN-based pseudo-complementary FET logic (PCFL) stage, which compensates the lack of complementary transistors by complementary logic signals. With this imitated CMOS behavior, static power losses are significantly reduced compared to a nMOS logic inverter. Simulations show that the addition PCFL buffer stage to a conventional driver stage (two nMOS logic inverter and final push-pull stage) enables an almost 10-fold reduction of static losses, while maintaining switching speed and area requirement. In addition, measurements of a PCFL stage illustrate low static power dissipation of < 2 μW. This buffer stage used in this concept enables gate driver losses of < 3.3 mW.