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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

: Sudarshan, Chirag; Lappas, Jan; Weis, Christian; Mathew, Deepak M.; Jung, Matthias; Wehn, Norbert


Pnevmatikatos, D.N.:
Embedded Computer Systems: Architectures, Modeling, and Simulation: 19th International Conference, SAMOS 2019. Proceedings : July 7–11, 2019, Samos, Greece
Cham: Springer, 2019 (Theoretical Computer Science and General Issues 11733)
ISBN: 978-3-030-27562-4
ISBN: 978-3-030-27561-7
International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS) <19, 2019, Samos>
European Commission EC
H2020; 732631; OPRECOMP
Fraunhofer IESE ()
DRAM; DDR3; Memory controller; Transprecision; PHY

Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting heterogeneous and approximate computing techniques. One of the recent evolution in this context is transprecision computing paradigm. The idea of the transprecision computing is to consume adequate amount of energy for each operation by performing dynamic precision reduction. The impact of the memory subsystem plays a crucial role in such systems. Hence, the energy efficiency of a transprecision system can be further optimized by tailoring the memory subsystem to the transprecision computing. In this work, we present a lean, low power, low latency memory controller that is appropriate for transprecision methodology. The memory controller consumes an average power of 129.33 mW at a frequency of 500 MHz and has a total area of 4.71 mm2 for UMC 65 nm process.