Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Getting To Tape-Out Quicker With Analog Layout Generators

Redaktionell betreuter Blog-Beitrag auf https://semiengineering.com, 07.10.2019
 
: Prautsch, Benjamin

:
Volltext (HTML; )

Online im WWW, 2019
Englisch
Online-Ressource, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Generators for schematics, test benches, simulation control, and layouts can significantly increase efficiency in the various design phases.
All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands but are necessary and take up a great deal of time in the design stage. Can automation help to save time here?

: http://publica.fraunhofer.de/dokumente/N-559274.html