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Process and design optimization of SiC MOSFET for low on-state resistance

Presentation held at Europe-Korea Conference on Science and Technology, EKC 2019, July 15-18, 2019, Vienna, Austria
 
: Sledziewski, Tomasz; Erlbacher, Tobias; Bauer, Anton

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Präsentation urn:nbn:de:0011-n-5524894 (1.4 MByte PDF)
MD5 Fingerprint: f95a0a4fbf5ecb75dfc80fe7324c3d65
Erstellt am: 31.7.2019


2019, 13 Folien
Europe-Korea Conference on Science and Technology (EKC) <12, 2019, Vienna>
Englisch
Vortrag, Elektronische Publikation
Fraunhofer IISB ()
silicon carbide; semiconductor; 4H-SiC; MOSFET

Abstract
Due to outstanding material parameters, silicon carbide (SiC) power devices offer much better electrical and thermal parameters than comparable silicon power devices in the same blocking voltage range. One of the key parameters of the power MOSFET is its on-state resistance, RDS(on) which has to be small, in order to obtain small power loss in a forward current conduction mode. In this work we present how process and design of SiC MOSFET can be optimized for the low on-state resistance. We distinguish different components of the total on-state resistance, which are the substrate and drift resistance; the channel, accumulation and JFET resistance; the source and contact resistance; and we show how each of these components has been minimized for our devices by the recent process developments. In addition to the process optimization, we discuss various ways to improve the SiC MOSFET design, which in general lead to larger cell integration and result in the lower on-state resistance of the device. These are for example a usage of a square elementary cell and an application of the short-channel technology. Results presented in this work are the experimental and simulation data collected during the academic, industrial and joint-research projects at Fraunhofer IISB.

: http://publica.fraunhofer.de/dokumente/N-552489.html