Publica
Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten. Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits
| Gammon, Peter M.:
Silicon Carbide and Related Materials 2018 : Selected papers from the 12th European Conference on Silicon Carbide and Related Materials (ECSCRM 2018), held in Birmingham, UK, in September 2018
Durnten-Zurich: TTP, 2019 (Materials Science Forum 963)
ISBN: 978-3-0357-1332-9
ISBN: 978-3-0357-2332-8
ISBN: 978-3-0357-3332-7
S.629-632 |
| European Conference on Silicon Carbide and Related Materials (ECSCRM) <12, 2018, Birmingham> |
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| Englisch |
| Konferenzbeitrag |
| Fraunhofer IISB () |
| charge compensation devices; LDMOS; RESURF; integrated circuit; 10 V-SiC-CMOS; silicon carbide |
Abstract
In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxial layer in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm2 for a device with a RESURF structure (REduced SURface Field) with a total implanted Al concentration of 6∙1016 cm-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).