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Electrical Limitations in Epitaxially Grown Kerfless Silicon Wafers for Solar Cells

: Schubert, M.C.; Beu, P.; Heinz, F.D.; Amiri, D.; Gust, E.; Steinhauser, B.; Janz, S.; Schindler, F.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 7th World Conference on Photovoltaic Energy Conversion, WCPEC 2018 : A Joint Conference of 45th IEEE PVSC, 28th PVSEC & 34th EU PVSEC, 10-15 June 2018, Waikoloa Village, HI, USA
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-8529-7
ISBN: 978-1-5386-8530-3
World Conference on Photovoltaic Energy Conversion (WCPEC) <7, 2018, Waikoloa/Hawaii>
Photovoltaic Specialists Conference (PVSC) <45, 2018, Waikoloa/Hawaii>
Photovoltaic Science and Engineering Conference (PVSEC) <28, 2018, Waikoloa/Hawaii>
European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC) <34, 2018, Waikoloa/Hawaii>
Fraunhofer ISE ()
Photovoltaik; Silicium-Photovoltaik; Charakterisierung von Prozess- und Silicium-Materialien; epitaxy; fault; photovoltaics; kerfless; quantification

In this work a quantitative approach to assess the specific material related efficiency limits of epitaxially grown silicon wafers is demonstrated. Based on experimental results of injection dependent carrier lifetime images on these wafers the absolute losses of identified defects, namely decorated stacking faults, defects from inhomogeneous processing and underlying homogeneously distributed recombination centers, have been quantified and compared. The losses from decorated stacking faults have been determined as a function of their lateral density. The obtained loss diagrams allow for systematic material optimization.