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A Security Architecture for RISC-V based IoT Devices

: Auer, Lukas; Skubich, Christian; Hiller, Matthias


European Design Automation Association -EDAA-:
Design, Automation & Test in Europe, DATE 2019. Proceedings : 25 - 29 March 2019, Florence, Italy
Piscataway, NJ: IEEE, 2019
ISBN: 978-3-9819263-3-0
ISBN: 978-3-9819263-2-3
ISBN: 978-1-7281-0331-0
Design, Automation & Test in Europe Conference & Exhibition (DATE) <23, 2019, Florence>
Sächsische Aufbaubank - Förderbank SAB
100317397; USeP
Universelle Sensor-Plattform
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Fraunhofer AISEC ()
RISC-V; device security; secure boot; watchdog timer

New IoT applications are demanding for more and more performance in embedded devices while their deployment and operation poses strict power constraints. We present the security concept for a customizable Internet of Things (IoT) platform based on the RISC-V ISA and developed by several Fraunhofer Institutes. It integrates a range of peripherals with a scalable computing subsystem as a three dimensional Systemin- Package (3D-SiP). The security features aim for a medium security level and target the requirements of the IoT market. Our security architecture extends given implementations to enable secure deployment, operation, and update. Core security features are secure boot, an authenticated watchdog timer, and key management. The Universal Sensor Platform (USeP) SoC is developed for GLOBALFOUNDRIES’ 22FDX technology and aims to provide a platform for Small and Medium-sized Enterprises (SMEs) that typically do not have access to advanced microelectronics and integration know-how, and are therefore limited to Commercial Off-The-Shelf (COTS) products.