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Dynamic Bending Reliability Analysis of Flexible Hybrid Integrated Chip-Foil Packages

: Palavesam, Nagarajan; Yacoub-George, E.; Hell, W.; Landesberger, C.; Kutter, C.; Bock, K.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 20th Electronics Packaging Technology Conference, EPTC 2018 : 4-7 December 2018, Singapore
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-7668-4
ISBN: 978-1-5386-7667-7
ISBN: 978-1-5386-7669-1
Electronics Packaging Technology Conference (EPTC) <20, 2018, Singapore>
European Commission EC
H2020; 692482; EnSO
Fraunhofer EMFT ()
flexible interposer; fatigue reliability; ultra-thin silicon

With the emergence of the Internet-of-Things (IoT) and wearable devices in the recent years, Flexible Hybrid Electronics (FHEs) has attracted significant attention. Chip-foil packages (also known as flexible interposers) fabricated by integrating ultra-thin silicon ICs onto or embedded into polymer foils comprising of metal interconnects (wiring lines, through hole via interconnects etc.) for powering up the system and transmission of data signals / IO commands are ideal candidates for FHE integration. The principal advantages of chip-foil packages over standard Surface Mount Device (SMD) components are their bend ability and conformability. However, the behavior of chip-foil packages under repeated bending must be analyzed in detail through extensive investigations to enable the transfer of the technology from research labs to industrial manufacturing platforms. Hence, we conducted two different types of bending tests to examine the repeated or dynamic bending reliability of the wiring lines and the via interconnects of the chip-foil packages. The experimental results highlight the need for design optimized dimensioning of the wiring lines and the via interconnects for manufacturing FHEs with high performance and good dynamic bending reliability. Such results complement the state-of-the-art information available regarding the electrical as well as mechanical reliability of chip-foil packages and are required as essential information for establishing guidelines for handling chip-foil packages during integration as well as for producing FHEs that are more reliable.