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Efficient coding scheme for DDR4 memory subsystems

 
: Kraft, Kira; Mathew, Deepak M.; Sudarshan, Chirag; Jung, Matthias; Weis, Christian; Wehn, Norbert; Longnos, Florian

:

Jacob, B. ; Association for Computing Machinery -ACM-:
International Symposium on Memory Systems, MEMSYS 2018. Proceedings : Alexandria, Virginia, October 01 - 04, 2018
New York: ACM, 2018
ISBN: 978-1-4503-6475-1
S.148-157
International Symposium on Memory Systems (MEMSYS) <2018, Alexandria/Va.>
European Commission EC
H2020; 732631; OPRECOMP
Open transPREcision COMPuting
Englisch
Konferenzbeitrag
Fraunhofer IESE ()
DBI; DRAM; error correction code (ECC); error mitigation

Abstract
DRAMs face several major challenges: On the one hand, DRAM bit cells are leaky and must be refreshed periodically to ensure data integrity. Therefore, DRAM devices suffer from a large overhead due to refreshes both in terms of performance (available bandwidth) and power. On the other hand, reliability issues caused by technology shrinking are becoming a large concern. Thus, ECC techniques for DRAM errors, and especially for retention errors, gain more and more importance. In this paper, we present an investigation on DRAM errors and derive a detailed model for these types of errors. The model is verified by various measurements, and analyzed from an information theory point of view. Based on this model, a scheme is presented that largely improves DRAM's reliability with low overhead.

: http://publica.fraunhofer.de/dokumente/N-534993.html