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Integrated Flow for Reverse Engineering of Nanoscale Technologies

Integrierter Prozess für die Rekonstruktion von nanoskaligen Halbleiterbausteinen
 
: Lippmann, Bernhard; Werner, Michael; Unverricht, Niklas; Singla, Aayush; Egger, Peter; Dübotzky; Rasche, Martin; Kellermann, Oliver; Gieser, Horst; Graeb, Helmut

Shibuya, Toshiyuki:
Proc. of 24th Asia and South Pacific Design Automation Conference
2019
1-8
24th Asia and South Pacific Design Automation Conference
BMBF
Selbstbestimmt und sicher in der digitalen Welt; KIS6HWS022; SyPASS
Englisch
Konferenzbeitrag
Fraunhofer EMFT ()
Reverse Engineering; Image processing: Netlist Extraction; Chip Scanning

Abstract
In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing need for an effective and efficient process of reverse engineering. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the extraction of a layout. For the first time the error between the generated layout and the known drawn GDS2 will be compared quantitatively as a figure of merit(FOM). From this layout a circuit graph of an ECC encryption and the partitioning in circuit blocks will be extracted.

: http://publica.fraunhofer.de/dokumente/N-531365.html