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Process variability - technological challenge and design issue for nanoscale devices

: Lorenz, Jürgen; Bär, Eberhard; Barraud, Sylvain; Brown, Andrew R.; Evanschitzky, Peter; Klüpfel, Fabian; Wang, Liping

Volltext ()

Micromachines 10 (2019), Nr.1, Art. 6, 16 S.
ISSN: 2072-666X
European Commission EC
H2020; 688101; SUPERAID7
Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node
Zeitschriftenaufsatz, Elektronische Publikation
Fraunhofer IISB ()
process simulation; device simulation; compact model; process variation; systematic variation; statistical variation; FinFET; nanowire; nanosheet

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.