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1.8 V second-order sigma delta modulator in 0.18 µm CMOS technology

: Carillo, J.M.; Montecelo, M.A.; Neubauer, H.; Hauer, J.; Duque-Carillo, J.F.


O'Regan, F. ; National University of Ireland, Dublin:
European Conference on Circuit Theory and Design 2005. Proceedings. Vol.1 : Cork, Ireland, 28 August - 2 September, 2005
Piscataway, NJ: IEEE, 2005
ISBN: 0-7803-9066-0
S.I/197- I/200
European Conference on Circuit Theory and Design (ECCTD) <17, 2005, Cork>
Fraunhofer IIS ()

This paper deals with the design of a second-order Sigma Delta modulator in 0.18-/spl mu/m CMOS technology. The A/D converter structure combines a 1-bit approach along with a relatively high oversampling ratio in order to obtain a reasonable dynamic range. A circuit prototype, including the modulator itself, a current reference, and the clock signals generator, has been fabricated to operate with a 1.8-V supply. A measured SNDR equal to 87 dB is obtained for a clock frequency equal to 8 MHz, while the experimental performance of the Sigma Delta modulator is maintained in a frequency range higher than 16 MHz.