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Performance analysis of high-speed MOS transistors with different layout styles

: Lopez, P.; Oberst, M.; Neubauer, H.; Hauer, J.; Caballo, D.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Circuits and Systems Society:
IEEE International Symposium on Circuits and Systems, ISCAS 2005. Conference proceedings. Vol.4 : May 23 - 26, 2005, International Conference Center, Kobe, Japan
Piscataway, NJ: IEEE Service Center, 2005
ISBN: 0-7803-8834-8
IEEE International Symposium on Circuits and Systems (ISCAS) <2005, Kobe>
Fraunhofer IIS ()

Several layout schemes for MOS transistors have been investigated and compared in terms of speed and layout area. Among them, the so-called closed, donut or doughnut transistors have been characterized, obtaining an analytical expression for the calculation of the equivalent W/L ratio for a general n-side regular polygonal-shape. The comparisons show that with quasi-minimum dimension transistors and L=0.35 mum, reductions of up to 81% on the drain area can be achieved with an increase of only a 10% on the total layout area for given W and L. An application improving the switching speed of an output multiplexer is shown.