Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Development of an Ozone-Based Inline Cleaning and Conditioning Concept

 
: Fischer, A.; Moldovan, A.; Temmler, J.; Zimmer, M.; Rentsch, J.

:
Postprint urn:nbn:de:0011-n-5254693 (547 KByte PDF)
MD5 Fingerprint: 8363b6addee76d27b8547b0bd6e74824
Copyright AIP
Erstellt am: 25.1.2019


Ballif, C. ; American Institute of Physics -AIP-, New York:
SiliconPV 2018, 8th International Conference on Crystalline Silicon Photovoltaics : 19-21 March 2018, Lausanne, Switzerland
Woodbury, N.Y.: AIP, 2018 (AIP Conference Proceedings 1999)
ISBN: 978-0-7354-1715-1
Art. 050001, 7 S.
International Conference on Crystalline Silicon Photovoltaics (SiliconPV) <8, 2018, Lausanne>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer ISE ()
Photovoltaik; Silicium-Photovoltaik; Oberflächen-Konditionierung; Passivierung; Lichteinfang; inline; based cleaning; conditioning; etch back

Abstract
In this work, a cleaning and conditioning process consisting of ozonized water, hydrofluoric and hydrochloric acid in concentrations below 1 wt% is implemented within an inline wet chemical processing tool. This inline process is characterized and compared to the cleaning and conditioning process inside a batch process tool. The resulting process homogeneity, the optical properties of the wafer surface after cleaning and conditioning inside the inline wet chemical processing tool and the resulting surface defects after passivation with intrinsic amorphous silicon is investigated. On large area Czochralski wafers a high degree of process homogeneity after an emitter etch back with standart deviation values below 5% are shown. Furthermore implied open circuit voltages above 740 mV after passivation with amourphes intrinsic Silicon are reached. In the end, system-specific optimization options are presented in order to achieve a more homogeneous process, which is capable of removing the phosphor silicate glass layer, perform an adjusted emitter etch back and leave a clean and defect free wafer interface in just one process step.

: http://publica.fraunhofer.de/dokumente/N-525469.html