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Heterogeneous integration of vertical GaN power transistor on Si capacitor for DC-DC converters

Presentation held at ESTC 2018, IEEE 7th Electronics System-Integration Technology Conference, September 18th-21st, 2018, Dresden, Germany
 
: Yu, Zechun; Zeltner, Stefan; Boettcher, Norman; Rattmann, Gudrun; Leib, Jürgen; Bayer, Christoph Friedrich; Schletz, Andreas; Erlbacher, Tobias; Frey, Lothar

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Präsentation urn:nbn:de:0011-n-5215097 (1.7 MByte PDF)
MD5 Fingerprint: 9e7743b2c94737c9ed7854a2228cdac3
Erstellt am: 7.12.2018


2018, 22 Folien
Electronics System-Integration Technology Conference (ESTC) <7, 2018, Dresden>
Englisch
Vortrag, Elektronische Publikation
Fraunhofer IISB ()
vertical GaN; Si-capacitor; Ag-Ag direct bonding; 3D integration

Abstract
Point of load (PoL) converters are emerging as common solution for industrial applications, telecommunications, server, and aerospace. In this work, a topology is designed for a single stage 48 V to 1 V PoL converter by using new gallium nitride (GaN) devices and integrated silicon capacitors. Various wafer-level packaging concepts such as die-to-wafer bonding, wafer-level thinning, and through-silicon via (TSV) will be presented and discussed based on this topology. Furthermore, two novel devices will be developed and used for the packaging concepts. One is a GaN transistor with vertical channel, which will exhibit significantly lower power losses when switching and converting power. The other is an integrated silicon capacitor with lateral geometry, in which positive and negative electro des are insulated from the substrate and formed on the same side. Simulation is performed to compare the parasitic inductance from the different concepts. A direct bonding process is shown to provide flexibility in engineering new device geometries and can be exploited to mitigate the electrical parasitics.

: http://publica.fraunhofer.de/dokumente/N-521509.html