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Heterogeneous interposer based integration of chips onto interposer to achieve high speed interfaces for ADC application

: Chaudhary, M.W.; Heinig, A.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 19th Electronics Packaging Technology Conference, EPTC 2017 : 6-9 December 2017, Singapore
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-3042-6
ISBN: 978-1-5386-3041-9
ISBN: 978-1-5386-3043-3
Electronics Packaging Technology Conference (EPTC) <19, 2017, Singapore>
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Integration and miniaturization has recently led to the passive silicon interposer based 2.5D integration and through silicon via based 3D integration. These integration technologies offer hundreds of highly dense chip to chip interconnects, which is a mandatory requirement for Wide-IO and High bandwidth memory (HBM) interfaces. But these memory interfaces require per channel bandwidth of around 2Gbps which can be achieved with less wide interconnects. But for high speed serial interfaces, it is to be seen how the interposer interconnect will perform and how wide interconnect should be. This paper focuses on high speed serial circuits' performance on interposer channels and discusses the energy, bandwidth, and area tradeoffs in interposer based chip to chip serial interface.