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Packaging meets heterogeneous integration driving direction for advanced system in packages

: Wolf, M.J.; Steller, W.; Lang, K.-D.


Institute of Electrical and Electronics Engineers -IEEE-:
Pan Pacific Microelectronics Symposium, Pan Pacific 2018 : 5-8 Feb. 2018, Waimea, HI, USA
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-944543-04-4
ISBN: 978-1-944543-05-1
ISBN: 978-1-5386-4767-7
Pan Pacific Microelectronics Symposium <2018, Waimea/Hawaii>
Fraunhofer IZM ()

Heterogeneous integration of different devices by using 3D architectures allows the realization of application specific System in Packages (SiP) with a high functionality in a cost effective way. Enabling building blocks technologies are substrate-, interconnect-, assembly- and device integration technologies to integrate sensors, ASICs, transceiver, memories and passive elements. SiPs based on interposer architectures are very attractive due to system performance improvements and due to optimized form factor achievements on wafer level.