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Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction

 
: Lefeuvre, T.; Fassi, I.; Cullmann, C.; Gebhard, G.; Kasnakli, E.K.; Puaut, I.; Derrien, S.

:

Madsen, J. ; European Design Automation Association -EDAA-; Institute of Electrical and Electronics Engineers -IEEE-, Council on Electronic Design Automation; European Electronic Chips & Systems design Initiative -ECSI-, Gieres; Association for Computing Machinery -ACM-, Special Interest Group on Design Automation -SIGDA-:
Design, Automation & Test in Europe, DATE 2018. Proceedings : 19-23 March 2018, Dresden, Germany
Piscataway, NJ: IEEE, 2018
ISBN: 978-3-9819263-0-9
ISBN: 978-3-9819263-1-6
S.925-930
Design, Automation & Test in Europe Conference & Exhibition (DATE) <21, 2018, Dresden>
Englisch
Konferenzbeitrag
Fraunhofer IIS ()

Abstract
The ARGO H2020 European project aims at developing a Worst-Case Execution Time (WCET)-aware parallelizing compilation toolchain. This toolchain operates on Scilab and XCoS inputs, and targets ScratchPad memory (SPM)-based multi-cores. Data-layout and loop transformations play a key role in this flow as they improve SPM efficiency and reduce the number of accesses to shared main memory. In this paper 1 , we study how these transformations impact WCET estimates of sequential codes. We demonstrate that they can bring significant improvements of WCET estimates (up to 2.7 χ) provided that the WCET analysis process is guided with automatically generated flow annotations obtained using polyhedral counting techniques.

: http://publica.fraunhofer.de/dokumente/N-520432.html