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High speed interfaces for chip to chip communication on interposer based integration

 
: Chaudhary, M.W.; Heinig, A.

:

Dziedzic, A. ; Institute of Electrical and Electronics Engineers -IEEE-; International Microelectronics and Packaging Society -IMAPS-, Poland Chapter:
21st European Microelectronics Packaging Conference, EMPC 2017. Proceedings : Warsaw, 10-13 September 2017
Piscataway, NJ: IEEE, 2017
ISBN: 978-0-9568086-4-6
ISBN: 978-1-5386-2309-1
S.233-236
European Microelectronics Packaging Conference (EMPC) <21, 2017, Warsaw>
Englisch
Konferenzbeitrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Interposer can offer higher number of interconnect and overall larger bandwidth per unit area and watts as compared to PCB based systems. One of the most commonly discussed high speed interfaces are the memory to processor interfaces which run at high clock rates and transfer data without error. There are a number of constraints to designing these memory systems in PCBs especially the correctly matched on die terminations which not only costs silicon area on the memory die but also costs a lot of power. In this work, it will be shown that silicon interposer based interfaces can support the high speed memory interfaces and can meet the electrical specifications of such interfaces while saving a lot of area. DDR3 memory interface is used as the test case to prove this statement.

: http://publica.fraunhofer.de/dokumente/N-520425.html