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Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs

 
: Hesselbarth, R.; Wilde, F.; Gu, C.; Hanley, N.

:

IEEE Computer Society; IEEE Computer Society, Test Technology Technical Council -TTTC-; IEEE Computer Society, Technical Committee on Security and Privacy:
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018. Proceedings : April 30-4 May 2018, The Ritz-Carlton Washington DC, USA
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-4731-8
ISBN: 978-1-5386-4732-5
S.126-133
International Symposium on Hardware-Oriented Security and Trust (HOST) <11, 2018, Washington/DC>
Englisch
Konferenzbeitrag
Fraunhofer AISEC ()

Abstract
Runtime accessible, general purpose, secure secret storage based on physical unclonable functions (PUFs) implemented within the programmable logic fabric is one of the most interesting applications of PUFs on field programmable gate arrays (FPGAs). To properly evaluate the quality of a PUF design, data from a large number of devices is required. This work therefore publishes a dataset containing 100 repeated measurements of 6592 ring oscillators (ROs) on 217 Xilinx Artix-7 XC7A35T FPGAs. This is both larger, and based on a more recent technology node than other publicly available datasets of related work. Apart from making the raw data publicly available, a thorough analysis is performed. The location and type of slice is found to affect the RO frequency by approx. 5 MHz, fast switching logic decreases the frequency by approx. 10MHz, and ROs adjacent to clock routing resources showed an expected frequency of 20 MHz less than others on the device. We also address the time-to-response of ring oscillator PUFs (RO-PUFs), which can be large, by optimizing the evaluation time with regard to the measurement precision and found 70.71 μs to be optimal for the device and architecture under test. The temperature induced bit error rate was estimated to be 3.5 % and 5.8 % for temperature differences of 60 °C and 100 °C respectively. Finally, access to the FPGA array used to obtain the data will be granted to interested researchers.

: http://publica.fraunhofer.de/dokumente/N-520316.html