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Electrical Characterization of a High Speed HBM Interface for a Low Cost Interposer

: Dittrich, M.; Heinig, A.; Hopsch, F.


Karikalan, S. ; Institute of Electrical and Electronics Engineers -IEEE-:
68th Electronic Components and Technology Conference, ECTC 2018. Proceedings : 29 May-1 June 2018, San Diego, California
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-5000-4
ISBN: 978-1-5386-4999-2
ISBN: 978-1-5386-4998-5
Electronic Components and Technology Conference (ECTC) <68, 2018, San Diego/Calif.>
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

The demand for higher data rates is still ongoing. But the physical laws are limiting the recent approach of using higher and higher speeds. This leads to a switch from very high-speed on a limited number of ports to reduced speed but with much more ports in parallel. One example for doing this is the High-Bandwidth-Memory (HBM). The paper presents the results of a topology evaluation and the simulations results of the HBM interface to and ASIC across a low cost interposer. Furthermore the design process for a silicon interposer using an Assembly Design Kit is presented. Based on the simulation and the developed design process a system with an ASIC and 8 HBM dies assembled on an interposer was built.