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Comparison of CDM and CC-TLP robustness for an ultra-high speed interface IC

 
: Weber, Johannes; Fung, Rita; Wong, Richard; Wolf, Heinrich; Gieser, A. Horst; Maurer, Linus

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Institute of Electrical and Electronics Engineers -IEEE-; EOS/ESD Association Inc., Rome/N.Y.; IEEE Reliability Society:
40th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018. Proceedings : Reno, NV, USA, September 23-28, 2018
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5853-7302-4
ISBN: 978-1-5386-7409-3
9 S.
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) <40, 2018, Reno/Nev.>
Englisch
Konferenzbeitrag
Fraunhofer EMFT ()
CC-TLP; CDM; Capacitively Coupled Transmission Line Pulsing; charged device model; ESD; electrostatic discharge; high speed device; rise time; slew rate; critical stress parameter; pogo pin capacitance; picosecond domain; peak current map; integrated circuit; testing

Abstract
Challenging the limits of todays metrology and test setups for CDM and Capacitively Coupled Transmission Line Pulsing (CC-TLP), the study identifies critical stress parameters for a 25 Gbps communication device in the CDM-domain. Only CC-TLP stress in combination with a 33/63 GHz single shot oscilloscope was able to relate significant differences of failure current distributions to the rise time spread in the order of few tens of picoseconds and to obtain a conclusive sharp pass/fail transition at a certain peak current level.

: http://publica.fraunhofer.de/dokumente/N-520005.html