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TCAD-fitted ESD modelling using equivalent circuit elements

Presentation held at International Electrostatic Discharge Workshop 2018, Priorij Corsendonk, Belgium
 
: Scharf, Patrick; Sohrmann, Christoph

:
Präsentation urn:nbn:de:0011-n-5194594 (1.3 MByte PDF)
MD5 Fingerprint: d7e383a4b19311cb998fa77d8b2f7701
Erstellt am: 17.11.2018


2018, 24 Folien
International Electrostatic Discharge Workshop (ESD) <2018, Priorij Corsendonk>
Bundesministerium für Bildung und Forschung BMBF
16ES0301K; RESIST
Resilient Integrated Systems, Teilvorhaben: Methoden zur Analyse des Alterungs- und ESD-Verhaltens elektronischer Systeme
englisch
Vortrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Electrostatic discharge (ESD) can be considered as one of the main reliability risks of modern electronic systems and causes failure of semiconductor devices by an over current effect. In case of an ESD event the avalanche breakdown leads to a negative differential resistance and possibly to strongly localized current filamentation. Because of strong self-heating in a very localized spot this current filament causes damage due to gate oxide or junction breakdown. The self-heating then leads to a translational movement which extenuates the problem to some extent. To predict the effectiveness of an ESD protection solution on IC level, it can be desirable to include those effects in a nominal circuit simulation. Today, this non-linear electro-thermal problem is mostly solved by a physics-based device simulator such as TCAD (Technology Computer Aided Design). TCAD gives very accurate results, but has an intolerable runtime for a high amount of devices. To improve the performance and to enable a fast optimization process during the design phase of a protection structure, we suggest a physics-based compact model capturing the relevant effects such as self-heating, avalanche multiplication and filament motion occurring under ESD load. The major advantage is the possibility to include the model into a circuit simulation and verify IC protection solutions already during the design phase.

: http://publica.fraunhofer.de/dokumente/N-519459.html