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A new concept to compensate the loop gain variation in phase-locked loops for wideband microwave frequency ramp synthesis

: Delden, M. van; Pohl, N.; Musch, T.


Pasya, I. ; Institute of Electrical and Electronics Engineers -IEEE-:
IEEE Asia Pacific Microwave Conference, APMC 2017 : November 13-16, 2017, Renaissance Kuala Lumpur Hotel; Proceedings
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-0640-7
ISBN: 978-1-5386-0639-1
ISBN: 978-1-5386-0641-4
Asia Pacific Microwave Conference (APMC) <2017, Kuala Lumpur>
Fraunhofer FHR ()

Synthesizers for wideband, low noise, linear frequency ramps based on phase-locked loops (PLL) exhibit a wide variation of the loop gain if no compensation method is applied. We present a new compensation method based on a phase-frequency detector gain modulation avoiding an external logic control, additional phase noise and high hardware complexity. Based on measured characteristics of its components, a 60 GHz-PLL with the new compensation method has been simulated, reducing the loop gain variation by a factor of 6.2 and the maximum double-sideband RMS phase jitter from 0.0422 rad to 0.0320 rad.