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NBTI and HCI models for circuit level aging simulations in different EDA environments

Paper presented at ESREF 2018, 29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Aalborg, Denmark, October 1-5, 2018
: Velarde Gonzalez, Fabio Alberto; Lange, André; Crocoll, Sonja; Jancke, Roland

Volltext urn:nbn:de:0011-n-5160870 (1.0 MByte PDF)
MD5 Fingerprint: d8b3a096361f46f52d2fdb49db35a16d
Erstellt am: 8.11.2018

2018, 3 S.
Bundesministerium für Bildung und Forschung BMBF
Advanced Distributed Pilot Line for More-than-Moore Technologies
Vortrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

The significance of transistor degradation due to aging mechanisms such as BTI or HCI has increased significantly with the continuous scaling down of CMOS technologies and their presence in safety-critical systems. In order to deliver the reliable systems that the industry currently demands, it is necessary to apply aging simulations in IC design projects. However, the capabilities that are available strongly depend on the EDA environment and tools. In this paper we present the work done in a case study to characterize and model NBTI and HCI degradation for X-FAB’s XU035 technology, and we discuss a methodology developed to implement and integrate user-defined aging models for circuit level simulation with consistent results across different design environments.