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Improving the error behavior of DRAM by exploiting its Z-channel property

 
: Kraft, Kira; Sudarshan, Chirag; Mathew, Deepak M.; Weis, Christian; Wehn, Norbert; Jung, Matthias

:

Madsen, J. ; European Design Automation Association -EDAA-; Institute of Electrical and Electronics Engineers -IEEE-, Council on Electronic Design Automation; European Electronic Chips & Systems design Initiative -ECSI-, Gieres; Association for Computing Machinery -ACM-, Special Interest Group on Design Automation -SIGDA-:
Design, Automation & Test in Europe, DATE 2018. Proceedings : 19-23 March 2018, Dresden, Germany
Piscataway, NJ: IEEE, 2018
ISBN: 978-3-9819263-0-9
ISBN: 978-3-9819263-1-6
S.1492-1495
Design, Automation & Test in Europe Conference & Exhibition (DATE) <21, 2018, Dresden>
European Commission EC
H2020; 732631; OPRECOMP
Open transPREcision COMPuting
Englisch
Konferenzbeitrag
Fraunhofer IESE ()
random access memory; channel model; error correction code; reliability; measurement uncertainty; channel capacity; reverse engineering

Abstract
In this paper, we present a new communication theoretic channel model for Dynamic Random Access Memory (DRAM) retention errors, that relies on the fully asymmetric retention error behavior of DRAM cells. This new model shows that the traditional approach is over pessimistic and we confirm this with real measurements of DDR3 and DDR4 DRAM devices. Together with an exploitation of the vendor specific true- and anti-cell structure, a low complexity bit-flipping approach is presented, that can largely increase DRAM's reliability with minimum overhead.

: http://publica.fraunhofer.de/dokumente/N-515801.html