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Process variability for devices at and beyond the 7 nm node

: Lorenz, Juergen; Asenov, Asen; Baer, Eberhard; Barraud, Sylvain; Kluepfel, Fabian; Millar, Campbell; Nedjalkov, Mihail

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ECS journal of solid state science and technology : jss 7 (2018), Nr.11, S.P595-P601
ISSN: 2162-8769
ISSN: 2162-8777
European Commission EC
H2020; 688101; SUPERAID7
Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node
Zeitschriftenaufsatz, Elektronische Publikation
Fraunhofer IISB ()
silicon electron device; CMOS transistor; compact model; process variation

Advanced CMOS devices are increasingly affected by various kinds of process variations. Whereas the impact of statistical process variations such as Random Dopant Fluctuations has for several years been discussed in numerous publications, the effect of systematic process variations which result from non-idealities of the equipment used or from various layout issues has got much less attention. Therefore, in the first part of this paper, an overview of the sources of process variability is given. In order to assess and minimize the impact of variations on device and circuit performance, relevant systematic and statistical variations must be simulated in parallel, from equipment through process to device and circuit level. Correlations must be traced from their source to the final result. In this paper the approach implemented in the cooperative European project SUPERAID7 to reach these goals is presented.