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Innovative packaging concepts for ultra thin integrated circuits

: Klink, G.; Feil, M.; Ansorge, F.; Aschenbrenner, R.; Reichl, H.

Electronic Components, Assemblies, and Materials Association; Components, Packaging and Manufacturing Technology Society -CPMT-:
ECTC 2001. Proceedings of the 51st Electronic Components & Technology Conference
Orlando/FL: Piscataway, 2001
ISBN: 0-7803-7040-6
Electronic Components and Technology Conference (ECTC) <51, 2001,Orlando/Fla.>
Englisch, Englisch
Fraunhofer IZM ()
wafer thinning; smart label; dicing by thinning; flexible circuit; thin silicon; assembly

The increasing demand on miniaturized and flat packaging technologies is driven by the trend towards small and portable electronic systems. Due to the requirements of modern Ball Grid Arrays, Smart Cards or Chip Size Packages thickness of integrated circuits has been reduced considerably compared with original wafer thickness. Driven by this evolution, the Fraunhofer Institute for Reliability and Microintegration has advanced its wafer thinning technology down to a residual silicon thickness of 20 µm and below. Because of low height, low topography of assembled chips and mechanical flexibility, these chips are ideal for integration in thin and bendable systems or vertically stacked systems. The advantages of thin ICs open a large field of new and interesting applications in microelectronics. However wafer thinning has its impact on subsequent assembly process. Dicing, handling, mounting and interconnection processes of thin ICs has to fulfil particular requirements, but also offers new and innovative solutions. These are investigated and discussed in this paper.