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The effect of etching and deposition processes on the width of spacers created during self-aligned double patterning

: Baer, Eberhard; Lorenz, Juergen

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Institute of Electrical and Electronics Engineers -IEEE-; IEEE Electron Devices Society:
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018. Proceedings : 24-26 September 2018, Austin, Texas, USA
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-6790-3
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) <2018, Austin/Tex.>
European Commission EC
H2020; 688101; SUPERAID7
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IISB ()
self-aligned double patterning; topography process simulation; deposition; etching; process variation

Topography process simulation has been used to study the interaction of etching and deposition processes for spacer creation for self-aligned double patterning (SADP). For the deposition process, the influence of the layer conformality was investigated. For the etching process, the directionality of the ion flux was varied. The simulations show that by an appropriate combination of the deposition and etching processes, spacers can be created with the desired critical dimension (CD) and a small deviation between the inner and outer spacer CD values. In addition to using the simulation flow for tuning the processes, it can be employed to investigate the influence of variations. As an example, we studied the effect of the across-wafer non-uniformity of the thickness of the deposited oxide lay er. For the process sequence considered, the relative change of the spacer CD is 4 to 5 times larger than the relative change of the oxide thickness.