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Ultra-low-power SAR ADC in 22 nm FD-SOI technology using body-biasing

 
: Jotschke, Marcel; Rao, Sunil Satish; Prautsch, Benjamin; Reich, Torsten

:
Postprint urn:nbn:de:0011-n-5127294 (2.2 MByte PDF)
MD5 Fingerprint: 05f65b58440ab5348b322ec1e40c70b2
Erstellt am: 19.9.2019


VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-:
ANALOG 2018. MEET YOUR CAD GUY/ MEET YOUR DESIGNER : Beiträge der 16. GMM/ITG-Fachtagung, 13. - 14. September 2018 in München/Neubiberg, CD-ROM
Berlin: VDE-Verlag, 2018 (GMM-Fachbericht 91)
ISBN: 978-3-8007-4754-2
ISBN: 3-8007-4754-5
S.46-50
Fachtagung "Analog" <16, 2018, Neubiberg>
Bundesministerium für Bildung und Forschung BMBF
16ESE0110S; PRIME
Lowest PoweR technologles and MEmory architectures for IoT
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Today’s sensor applications show a rising demand on miniaturized autonomous sensors nodes with extreme requirements on power dissipation. One core functionality of these sensor nodes is the conversion of analog sensor signals to digital data for post processing and data communication. In this work a 11 bit Successive Approximation Register (SAR) ADC with minimized power dissipation is developed for a modern 22 nm FDSOI technology. The design takes advantage of analog body biasing feature of FDSOI technology. It achieves a power dissipation of 5 µW at a sampling rate of 100 kS/s with an INL of ± 2.8 LSB without calibration. The ADC design is flexible and easy to migrate among technology nodes due to the use of generator-based Intelligent IP technology.

: http://publica.fraunhofer.de/dokumente/N-512729.html