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Full wafer redistribution and wafer embedding as key technologies for a multi-scale neuromorphic hardware cluster

: Zoschke, Kai; Güttler, M.; Böttcher, L.; Grübl, A.; Husmann, D.; Schemmel, J.; Meier, K.-H.; Ehrmann, O.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 19th Electronics Packaging Technology Conference, EPTC 2017 : 6-9 December 2017, Singapore
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-3042-6
ISBN: 978-1-5386-3041-9
ISBN: 978-1-5386-3043-3
Electronics Packaging Technology Conference (EPTC) <19, 2017, Singapore>
Fraunhofer IZM ()

Together with the Kirchhoff-Institute for Physics the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the Kirchhoff-Institute for Physics and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a high density reticle-to-reticle routing on 200 mm CMOS wafers. Neighboring reticles were interconnected across the scribe lines with an 8 μm pitch routing based on semi-additive copper metallization which was photo defined by full field mask aligning equipment. Passivation by photo sensitive benzocyclobutene (BCB) was used to enable a second intra-reticle routing layer. Final IO pads of nickel with flash gold were generated on top of each reticle. For final electrical connection the wafers were placed into mechanical fixtures and the IOs of all reticles were touched by elastomeric connectors. With that concept neuromorphic systems based on full wafers could be assembled and tested. The fabricated high density inter-reticle routing revealed a very high yield of larger than 99.9 %. In order to allow an upscaling of the system size to a large number of wafers with feasible effort a full wafer embedding concept for printed circuit boards was developed and proven in the second phase of the project. The wafers were thinned to 250 μm and laminated with additional prepreg layers and copper foils into a core material. A 200 mm circular cut was done into the core material and the inner prepreg layers to create the required clearance for the wafer. After lamination of the PCB panel the reticle IOs of the embedded wafer were accessed by micro via drilling, copper electroplating, lithography and subtractive etching of the PCB wiring structure. The created wiring with 50 μm line width enabled an access of the reticle IOs on the embedded wafer as well as a board level routing. The panels with the embedded wafers were subsequently stressed with up to 1000 thermal cycles between 0 °C and 100 °C and have shown no severe failure formation over the cycle time.