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Brittle fracture and damage in bond pad stacks - a study of parameter influences in coupled XFEM and delamination simulation of nanoindentation

: Albrecht, J.; Auersperg, J.; Reuther, G.M.; Kudella, P.W.; Brueckner, J.; Rzepka, S.; Pufall, R.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 18th Electronics Packaging Technology Conference, EPTC 2016. Proceedings : 30. November - 3 December 2016, Singapore
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-4368-2
ISBN: 978-1-5090-4369-9
ISBN: 978-1-5090-4370-5
Electronics Packaging Technology Conference (EPTC) <18, 2016, Singapore>
Fraunhofer ENAS ()

Wire bonding as well as wafer probing can lead to oxide layer cracking in Backend of Line (BEOL) Bond Pad Stacks. This, along with metal migration into formed cracks, may lead to electrical failures. Mechanical loading conditions comparable to those during the wafer test and the wire bonding process can be achieved using a nanoindenter. This work addresses the finite element (FE) simulation of an indentation process during which a spherical tip imprints into a silicon nitride film. Based on experimental results we have established a FE-model using ABAQUS Standard™ that reproduces the experimentally observed load-displacement behavior. Introducing of the extended finite element method (XFEM) as well as a cohesive contact approach allow describing different failure modes observed in our experiments. The simulation results show dependencies on the used crack initiation criteria and fracture toughness properties. Resulting patterns of damage initiation and propagation and also fracture patterns will be discussed on the basis of 2D axisymmetric and 3D quarter symmetric models. The latter includes circumferential cracks on top of the silicon nitride film with directional crack initiation as well as interface delamination reproduced by means of the energy-based Cohesive Zone approach. The results of these investigations enable predicting and avoiding failures, such as oxide layer cracking during wire bonding or wafer testing.