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Implementation of sparse signal recovery on FPGA for ultrasonic NDT

: Grandinetti, C.; Kirchhof, J.; Krieg, F.; Roemer, F.; Ihlow, A.; Delgaldo, G.; Theado, H.; Osman, A.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Ultrasonics Symposium, IUS 2017 : 6-9 September 2017, Washington, DC, USA
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-3383-0
ISBN: 978-1-5386-3382-3
ISBN: 978-1-5386-3384-7
International Ultrasonics Symposium (IUS) <2017, Washington/DC>
Fraunhofer IIS ()
Fraunhofer IZFP ()

For several use cases of complex processing algorithms on ultrasound NDT data, it is mandatory to ensure real-time signal processing speed. This can be achieved by using e.g. a field programmable gate array (FPGA). Sparse signal recovery (SSR) and compressed sensing (CS) methods are used for superior reconstruction of flaws from compressed measurement data. SSR and CS are currently a hot research topic in various fields of application. However, they are not yet implemented for ultrasound NDT in a real-time manner.