Publica
Hier finden Sie wissenschaftliche Publikationen aus den FraunhoferInstituten. Role of parasitic capacitances in power MOSFET turnon switching speed limits: A SiC case study
 Institute of Electrical and Electronics Engineers IEEE; IEEE Power Electronics Society; IEEE Industry Applications Society: ECCE 2017, IEEE Energy Conversion Congress & Exposition : Cincinnati, Ohio, October 15, 2017 Piscataway, NJ: IEEE, 2017 ISBN: 9781509029983 ISBN: 9781509029976 ISBN: 9781509029990 S.13871394 
 Energy Conversion Congress and Exposition (ECCE) <9, 2017, Cincinnati/Ohio> 

 Englisch 
 Konferenzbeitrag 
 Fraunhofer IZM () 
Abstract
This paper describes the effect of MOSFET internal capacitances on the channel current during the turnon switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a noload condition (zero drain current), starting from different drainsource voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other nonidealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.