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SiC power module loss reduction by PWM gate drive patterns and impedance-optimized gate drive voltages

: Gerstner, H.; Heckel, T.; Endruschat, A.; Roßkopf, A.; Eckardt, B.; März, M.


Kaplar, B. ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Power Electronics Society; Power Sources Manufacturers Association -PSMA-; IEEE Electron Devices Society:
WiPDA 2017, 5th Annual IEEE Workshop on Wide Bandgap Power Devices & Applications : Albuquerque, NM, October 30-November 1, 2017
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-3117-1
ISBN: 978-1-5386-3116-4
ISBN: 978-1-5386-3118-8
Workshop on Wide Bandgap Power Devices and Applications (WiPDA) <5, 2017, Albuquerque/NM>
Fraunhofer IISB ()

This paper presents a novel procedure to determine the internal gate-source voltage inside a multi-chip power module using the example of a SiC half bridge module. Based on the lumped elements of the gate circuit calculated by a quasi-static electromagnetic simulation, each field-effect transistor is represented by a single, voltage dependent capacitor. The procedure is validated by clamped inductive switching measurements of a SiC power module. Moreover, it is applied to determine the maximum permissible gate-source voltage range in compliance with the manufacturer's voltage rating for a given driver-module combination. In this context a significant extension of the gate drive voltage range and thus an increase of efficiency using impedance specific PWM patterns is demonstrated.