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Stress reduction in high voltage MIS capacitor fabrication

 
: Banzhaf, S.; Kenntner, J.; Grieb, M.; Schwaiger, S.; Erlbacher, T.; Bauer, A.J.; Frey, L.; Frey, L.

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Institute of Electrical and Electronics Engineers -IEEE-:
19th International Symposium on Power Electronics, Ee 2017 : Novi Sad, Serbia, October 19th-21st, 2017
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-3502-5
ISBN: 978-1-5386-3501-8
ISBN: 978-1-5386-3503-2
S.49-51
International Symposium on Power Electronics (Ee) <19, 2017, Novi Sad>
Englisch
Konferenzbeitrag
Fraunhofer IISB ()

Abstract
Metal-insulator-semiconductor capacitors used as a RC snubber attenuate voltage overshoots which may occur during switching phases. These devices feature good temperature stability up to 200°C and can be integrated very close to power switches on the same transfer substrate. As the capacitors need to withstand high voltages in most applications, thick dielectric layers have to be used, causing significant amount of wafer bow during processing. A dielectric stress compensation structure on the back side of the wafers is therefore introduced and shown to reduce the resulting wafer bow by up to 50%. Planar MIS capacitors using a 1 μm thick dielectric layer stack achieve dielectric breakdown voltages of up to 1000 V along with capacitance densities of 5.4 nF/cm2. In comparison, devices with a dielectric layer thickness of 250 nm exhibit a capacitance density of 13.6 nF/cm2 and a resulting dielectric breakdown voltage of 250 V.

: http://publica.fraunhofer.de/dokumente/N-502457.html