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Cache attacks and countermeasures for NTRUEncrypt on MPSoCs: Post-quantum resistance for the IoT

 
: Sepulveda, J.; Zankl, A.; Mischke, O.

:

Alioto, M. ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Circuits and Systems Society:
30th IEEE International System on Chip Conference, SOCC 2017. Proceedings : September 05-08, 2017, Munich, Germany
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-4034-0
ISBN: 978-1-5386-4033-3
ISBN: 978-1-5386-4035-7
S.120-125
International System on Chip Conference (SOCC) <30, 2017, Munich>
Englisch
Konferenzbeitrag
Fraunhofer AISEC ()

Abstract
Public-key cryptography (PKC), widely used to protect communication in the Internet of Things (IoT), is the basis for establishing secured communication channels between multiple parties. The foreseeable breakthrough of quantum computers represents a risk for many PKC ecosystems. Almost all approaches in use today rely on the hardness of factoring large integers or computing (elliptic-curve) discrete logarithms. It is known that cryptography based on these problems can be broken in polynomial time by Shors algorithm, once a large enough quantum computer is built. In order to prepare for such an event, the integration of quantum-resistant cryptography on devices operating in the IoT is mandatory to achieve long-term security. Due to their limited resources, tight performance requirements and long-term life-cycles, this is especially challenging for Multi-Processor System-on-Chips (MPSoCs) operating in this context. At the same time, it must be provided that well-known implementation attacks, such as those targeting a cipher's execution time or its use of the processor cache, are inhibited, as they've successfully been used to attack cryptosystems in the pre-quantum era. Hence, this work presents an analysis of the security-critical polynomial multiplication routine within the NTRU algorithm and its susceptibility to timing and cache attacks. We also propose two different countermeasures to harden systems with or without caches against said attacks, and include the evaluation of the respective overheads. We demonstrate that security against timing and cache attacks can be achieved with reasonable overheads depending on the chosen parameters of NTRU.

: http://publica.fraunhofer.de/dokumente/N-502448.html