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InP DHBT-based monolithically integrated CDR/DEMUX IC operating at 80 Gbit/s

InP DHBT basierende monolithisch integrierte CDR/DEMUX-Schaltung mit einer Operationsgeschwindigkeit von 80 Gbit/s
 
: Makon, R.E.; Driad, R.; Schneider, K.; Ludwig, M.; Aidam, R.; Quay, R.; Schlechtweg, M.; Weimann, G.

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IEEE journal of solid-state circuits 41 (2006), Nr.10, S.2215-2223
ISSN: 0018-9200
Englisch
Zeitschriftenaufsatz
Fraunhofer IAF ()
InP-DHBT; CDR; VCO; linearer Phasendetektor; Schleifenfilter

Abstract
In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both f(ind T) and f(ind max). The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600 mV(ind pp). The extracted 40 GHz clock signal shows a phase noise as low as -98 dBc/Hz at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of -4.8 V, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.

: http://publica.fraunhofer.de/dokumente/N-49834.html